Workshop on Large-Scale Parallel Processing

to be held at the

IEEE International Parallel and Distributed Processing Symposium

Atlanta, Georgia

April 19th - 23rd 2010

Please join us in Atlanta for what promises to be a very interesting day. The Preliminary workshop schedule is now available and offers a full day of technical talks including analysis of GPU capabilities, node-level processor optimizations, and analysis of large-Scale systems.

We are also pleased to announce that this year's keynote will be given by Thom Dunning from the National Center for Supercomputing Applications (NCSA).

Blue Waters: An Extraordinary Computing Resource for Advanced Science & Engineering
Thom H. Dunning, Jr.
National Center for Supercomputing Applications, University of Illinois at Urbana-Champaign

Abstract


The workshop on Large-Scale Parallel Processing is a forum that focuses on computer systems that utilize thousands of processors and beyond. This is a very active area given the goals of many researchers world-wide to enhance science-by-simulation through installing large-scale multi-petaflop systems at the start of the next decade. Large-scale systems, referred to by some as extreme-scale and Ultra-scale, have many important research aspects that need detailed examination in order for their effective design, deployment, and utilization to take place. These include handling the substantial increase in multi-core on a chip, the ensuing interconnection hierarchy, communication, and synchronization mechanisms. The workshop aims to bring together researchers from different communities working on challenging problems in this area for a dynamic exchange of ideas. Work at early stages of development as well as work that has been demonstrated in practice is equally welcome.

Of particular interest are papers that identify and analyze novel ideas rather than providing incremental advances in the following areas:

Large-scale systems : exploiting parallelism at large-scale, the coordination of large numbers of processing elements, synchronization and communication at large-scale, programming models and productivity

Multi-core : utilization of increased parallelism on a single chip (MPP on a chip such as the Cell and GPUs), the possible integration of these into large-scale systems, and dealing with the resulting hierarchical connectivity.

Novel architectures and experimental systems : the design of novel systems, the use of processors in memory (PIMS), parallelism in emerging technologies, future trends.

Applications : novel algorithmic and application methods, experiences in the design and use of applications that scale to large-scales, overcoming of limitations, performance analysis and insights gained.

Results of both theoretical and practical significance will be considered, as well as work that has demonstrated impact at small-scale that will also affect large-scale systems. Work may involve algorithms, languages, various types of models, or hardware. A list of papers presented at previous LSPP workshops can be found here.

Selected work presented at the workshop will be published in a special issue of Parallel Processing Letters in late 2010. Special issues of Parallel Processing Letters from LSPP workshops previously appeared in December 2009 and 2008.


Submission Guidelines

Papers should not exceed eight single-space pages (including figures, tables and references) using a 12-point on 8½x11-inch pages. Submissions in PostScript or PDF should be made using EDAS. Informal enquiries can be made to djk@lanl.gov. Submissions will be judged on correctness, originality, technical strength, significance, presentation quality and appropriateness. Submitted papers should not have appeared in or under consideration for another venue.

Important Dates

Papers due: December 18th 2009 *** EXTENDED DEADLINE ***
Notification of acceptance: January 15th 2010
Camera-Ready Papers due: February 1st 2010

Workshop Organization

Workshop Co-chairs
Darren J. Kerbyson Los Alamos National Laboratory
Ram Rajamony IBM Austin Research Lab
Charles Weems University of Massachusetts

Additional Steering Committee Members
Johnnie Baker Kent State University
Alex Jones University of Pittsburgh
H.J. Siegel Colorado State University

Program Committee
Ghoerge Almasi IBM T.J. Watson Research Lab
Taisuke Boku University of Tsukuba, Japan
Marco Daneluto University of Pisa
Martin Herbordt Boston University
Lei Huang University of Houston
Daniel Katz University of Chicago
Jesus Labarta Barcelona Supercomputing Center, Spain
John Michalakes NCAR, Boulder
Pat McCormick Los Alamos National Laboratory
Celso Mendes University of Illinois Urbana-Champagne
Bernd Mohr Forschungszentrum Juelich, Germany
Stathis Papaefstathiou Microsoft Research
Michael Scherger Texas A&M University-Corpus Christi
Harvey Wasserman NERSC/LBNL
Gerhard Wellein University of Erlangen, Germany
Pat Worley Oak Ridge National Laboratory

Workshop General Chair and point of contact: Darren J. Kerbyson djk@lanl.gov