The 2nd Workshop on Communication Architecture for Scalable Systems
CASS 2012
To be held in conjunction with the
26th IEEE International Parallel and Distributed Processing Symposium (IPDPS 2012)

Shanghai, China, 21 May 2012

Workshop Organization

Co-chairs

Program Committee

Steering Committee

Theme

High-speed communication is critical to all parts of an HPC system. On-chip networks for emerging many-core processors; point-to-point interconnects, which have replaced the system bus for intra-node communication; and system-wide networks, which form the backbone of any large-scale parallel system, all contribute to the construction of the world’s fastest computers. Numerous research groups in academia, industry, and government are currently investigating the issues involved in improving the speed, reliability, power consumption, and other characteristics of communication subsystems and seeking new ways to advance the state of the art in cluster communication.

The goal of this workshop is to bring together researchers working on improving communication at every level of the network hierarchy (on-chip, intra-node, and cross-cluster), thereby enabling the sharing and adaptation of ideas from what have traditionally been separate communities.

Workshop Program

8:55 - 9:00 Welcome and workshop introduction
9:00 - 10:00 Keynote address
Speaker: Sameer Kumar, IBM TJ Watson Research Center
Title: Challenges of Exascale Messaging Library Design: Case Study with Blue Gene Machines
10:00 - 10:30 Break #1
10:30 - 12:00 Session I
Topic: Messaging Layers
Chair: Darius Buntinas, Argonne National Laboratory
  • On the Portability and Performance of Message-Passing Programs on Embedded Multicore Platforms
    Shih-Hao Hung, Po-Hsun Chiu, Chia-Heng Tu, Wei-Ting Chou, Wen-Long Yang
  • Optimized Reduce for Mesh-Based NoC Multiprocessors
    Adan Kohler, Martin Radetzki
  • Estimating Application Hierarchical Bandwidth Requirements using BSP Family Models
    Adrian Soviani, Jaswinder Pal Singh
12:00 - 1:30 Lunch (provided by IPDPS)
1:30 - 3:00 Session II
Topic: Routing and Data Transfer
Chair: T.B.D.
  • Design of Direct Communication Facility for Manycore-based Accelerators
    Min Si, Yutaka Ishikawa
  • Achieving Global Fairness for On-Chip Network Using Group Allocation
    Yarsun Hsu, Shan-Jung Miao
  • Limited Multi-path Routing on Extended Generalized Fat-trees
    Santosh K Mahapatra, Xin Yuan, Wickus Nienaber
3:00 - 3:30 Wrap up, adjourn, and break #2

Note: The CASS 2012 program page on EDAS provides an alternate formatting of the workshop program and includes talk abstracts and links to the papers.

Registration and Hotel Information

Workshop registration is handled by the IPDPS 2012 conference. There is a single registration for the conference and all of its 18 workshops. Please visit the IPDPS 2012 Web page for registration and hotel information.

Additional Information

E-mail Contact

For more information on CASS 2012 or if you have any questions please contact the workshop organizers at the e-mail address listed at the bottom of this page.

Call for Papers

Although the submission deadline has long since passed, the following links will take you to the CASS 2012 CFP:

Links to CASS and CAC workshops (CASS's predecessor)